1. Field of the Invention
The present invention relates to digital to analog conversion, and more particularly, to a digital to analog converter and a method of performing digital to analog conversion.
2. Description of the Related Art
FIG. 1 illustrates a circuit diagram of a conventional digital to analog converter. Referring to FIG. 1, the digital to analog converter (DAC) 10 includes a signal conversion block 12 and two sample-hold amplifiers 18 and 20.
The signal conversion block 12 includes a resistor string 14 connected between a first node receiving a first reference voltage Vref1 and a second node receiving a second reference voltage Vref2, where Vref2 may be smaller than Vref1, for generating multiple voltages. A selection circuit 16 outputs one of the voltages as a select voltage DECO in response to an input digital signal DATA.
The sample-hold amplifier 18 includes a sampling capacitor C1, multiple switches SW_SA, SW_NA and SW_FA, and an operational amplifier OP AMP. The sample-hold amplifier 20 includes a sampling capacitor C2, multiple switches SW_SB, SW_NB and SW_FB, and an operational amplifier OP AMP. The capacitors C1 and C2 may have the same capacitance or different capacitances.
To secure an RC time by a resistor value R of the signal conversion block 12 and a capacitance C of each capacitor C1 or C2 of the two sample-hold amplifiers 18 and 20, a channel driver (e.g., a DAC 10) embodied in each channel of a source driver requires the two sample-hold amplifiers 18 and 20 for outputting an output signal in every “line time,” which refers to the time for scanning a gate line.
Accordingly, the DAC 10 outputs a signal, which is held by a holding operation HOLD of the sample-hold amplifier 20, as an output signal DACB, while the sample-hold amplifier 18 performs a sampling operation SAMPLE during a first line time. The DAC 10 outputs a signal, which is held by a holding operation HOLD of the sample-hold amplifier 18, as an output signal DACA, while the sample-hold amplifier 20 performs a sampling operation SAMPLE during a second line time, which occurs after the first line time. In other words, the DAC 10 alternately outputs the output signals DACA and DACB of the two sample-hold amplifiers 18 and 20 in turn.
The conventional DAC 10 illustrated in FIG. 1 requires two sample-hold amplifiers 18 and 20, each of which consumes power. Also, each of the sample-hold amplifiers 18 and 20 includes an operational amplifier OP AMP, which is large and consumes a significant amount of static current.